Workers are familiar with document processing (e.g., check processors for automatic sort) that involve creating an electronic digital image of each document as it passes an imaging station (e.g., as simplistically illustrated in FIG. 1A). In FIG. 1A there is shown a financial document sorting system having a typical document sorter 12, which in the preferred embodiment of this invention, comprises a model DP1800 sorter which is manufactured by the UNISYS Corporation of Blue Bell, Pa.
Sorter 12 contains a track 14 along which a plurality of financial documents 16 (e.g., checks) passes. Sorter 12 includes a magnetic character reader 18 and magnetic strip character controller 20, as well as a document holder 22 and a pipelined image processor (imaging station) 24.
Controller 20 is coupled to reader 18 via signals on a bus 26, to a host computer 28 by signals on a bus 30, and to the pipelined image processor 24 by signals on a bus 32. A computer 28 is coupled to an image storage module 34 by signals on a bus 36, while image storage module 34 is also coupled to the pipelined image processor 24 and to a plurality of workstations 38 via signals on a buses 40 and 42, respectively.
In operation, documents 16 sequentially pass reader 18 which reads a typical code appearing upon the usual MICR codeline strip which is normally placed upon each of the documents 16. The code read-out is then sent to computer 28 by signals on bus 30 for storage therein, and also to processor 24 by signals on bus 32. As each document 16 further proceeds, it passes imaging station 24 which creates a digital electronic image of the document, and sends this processed image data, via signals on bus 40, to image storage module 34 for storage therein. After passing station 24, each document is then sorted, by sorter 12, in the usual way (based on the contents of the MICR codeline) and is held at document holder 22.
After a typical prescribed block of such documents 16 has been sorted as aforedescribed, workstations 38, via signals on bus 42, may sequentially request document image data from storage module 34. This image data is then downloaded to a workstation 38, via signals on bus 42, along with associated magnetic code data obtained from host computer 28.
After such image data is so captured at a workstation 38, an operator may electronically enter the dollar amount (e.g., courtesy amount) on each document and electronically resolve any associated inconsistencies. Each image's dollar amount and associated corrections then form a single record which is sent to computer 28, via signals on bus 42, where it may later be accessed for use in automatically inscribing the dollar amount and corrections upon the document. Therefore, the aforementioned document sort system 10 substantially eliminates manual handling of an individual document 16, once its associated dollar amount is so verified and inscribed, to thereby increase the efficiency, speed and timeliness of the overall document sorting system 10.
Compression Stages:
Within Image Processor 24 in FIG. 1A is placed one of "n" JPEG Processing/Compression stages (24-A). Two of these JPEG Processing/Compression paths are implemented on a Histogram/Compressor printed circuit board assembly (PCBA) shown in FIG. 1C.
According to a feature hereof, Image Processor 24 of FIG. 1 is characterized by an Image Digitizer unit (D of FIG. 2) for analog to digital conversion of the captured image, a Normalizer/Scaler (N/S Set, FIG. 2) for normalization, delineation and scaling of the video image, a set of "n", parallel JPEG Processing/Compression units (J1 of FIG. 2 and 24-A of FIG. 1) for image processing/JPEG compression and a JPEG Compressed Data Buffer unit (JCDB in FIG. 2) for collection and temporary storage of compressed images from the JPEG Processing/Compression units. [Note "JPEG" refers to a compression standard by the "Joint Photographic Experts Group".]
These functions are implemented especially to meet the performance requirements of a high speed check imaging system and to minimize the cost of the system by reducing the amount of "parallel hardware" needed to compress images. A preferred Processing/Compression Stage (for JPEG) is indicated in FIG. 1C.
The JPEG compression hardware performs image processing on a 128 grey level, scaled image before executing a two-pass JPEG compression. Scaling can range from 137.5 dpi to 50 dpi in steps of 12.5 dpi. This two-pass compression is designed--according to this feature--to reduce images to a predictable "packet size" apt for use in the entire high speed check imaging system. These functions of the JPEG "P/C" (Processing/Compression) hardware, (detailed below) must be performed, here, in real time on check images as they move down a high speed Check sorter track at an approximate rate of 1800 checks per minute.
It is not possible, within the environment of present high speed check-imaging systems (detailed below), for a single JPEG "P/C" (Processing/Compression) path to process every check in real time. Therefore, one needs multiple JPEG "P/C" paths, operating in parallel, are needed. To reduce the time required for each Processing/Compression path to operate on an image (and therefore reduce the number of parallel paths needed to maintain system performance), many of the required functions of the JPEG "P/C" path have been implemented in hardware. A detailed explanation of such functions is described below.
System Environment:
A JPEG "P/C" (process/compression) path as here contemplated, will perform image processing and real time JPEG compression of normalized and scaled images of documents (e.g. checks) captured in a check sorter at an average rate of 1800 checks per minute. The diagram in FIG. 2 indicates conditions under which the JPEG "P/C" path operates and the performance required of this unit to maintain overall system performance.
FIG. 2 shows the processing of a sample of check images as they move left to right across the page, similar to the way the checks would move through the check sorter. Here, track speed of the sorter assumed to be 300 inches per second. This means that a check that is 6 inches long will take 20 ms to pass a fixed point on the sorter track; here, checks can range in length from 5.75 inches to 9 inches (19 ms to 30 ms), with gaps between checks ranging from 1.5 inches (5 ms) to several inches).
The check images are captured by a camera preferably comprised of a vertical, 1024-element CCPD array which samples 256 grey levels per pixel (8 bits) with a resolution of 200 pixels per inch. In the vertical direction, the camera can capture images up to 5.12 inches high. The 1024 element array takes a snapshot of the check every 16.66 us as it moves down the sorter track, yielding a horizontal capture resolution of 200 pixels per inch. These 1024 pixel scans (captured every 16.66 us by the CCPD array) are divided into eight 128 pixel channels (shown as CH0 through CH7 in FIG. 2, each composed of 128 pixel scans). Hardware in the Camera/Digitizer D converts each 128 pixel scan into eight serial streams of pixels, with one pixel being output approximately every 130 ns.
The N/S (Normalizer/Scaler) hardware next normalizes the pixel values from the 1024 CCPD elements and then scales the image down. The maximum resolution after scaling is 137.5 (11/16ths scaling of 200 dpi captured image) pixels per inch in both dimensions (e.g., see example shown in FIG. 2). In this example the 128 pixel scans in each channel are reduced to 88 pixels per scan. The N/S hardware "time-multiplexes" four channels' worth of data onto two, 8-bit serial outputs to the JPEG "P/C" hardware. The 88 pixels from all four "even-numbered" (total of 352 pixels per scan at 137.5 dpi) channels (0, 2, 4, 6) are time-multiplexed along one serial stream, while the pixels from the four "odd" channels (1, 3, 5 and 7) are multiplexed along a second serial stream. The two serial pixel streams operate at 50 ns/pixel (20 MHz) to guarantee that all 352 pixels per scan on each serial path can be transferred to the JPEG "P/C" hardware before the next scan is transferred.
A pair of JPEG "P/C" paths are preferably implemented on an H/C PCB (Histogram/Compressor printed circuit board, as indicated in FIG. 1C). Each process/compression path must detect the image dimensions and perform image processing on the scaled image prior to compression. Selected image processing algorithms require a grey level histogram of the entire image prior to execution. This means the entire image must be buffered (e.g., at 3-1, FIG. 3) and a histogram generated (e.g., at 3-7) before image processing can begin. Once image processing is complete, compression can begin.
The performance of the entire image system is what dictates how the JPEG Processing/Compression hardware must reduce each image to a target packet size; this is why the here-detailed JPEG compression hardware embodiment executes a 2-pass compression. The first pass uses a "standard" QM (Quantization Matrix) for JPEG compression. The results of the first pass compression, as well as the detected image dimensions, are used to pick a second QM for a second, final compression that will reduce the scaled image to the desired compressed packet size.
To maintain system performance, the JPEG Processing/Compression hardware must perform all these functions in real time which equates to generating a JPEG compression packet in 20 ms for a 6-inch check. Because a single JPEG "P/C" path cannot meet these requirements, multiple paths operating in parallel are required. The described H/C PCB was equipped with two independent JPEG "P/C" paths for this purpose (see FIGS. 3, 1C), and the system has locations for up to 8 H/C PCBs (for Front/Rear imaging). This means the system can have as many as 16 JPEG compression paths operating in parallel (e.g. two for each H/C PCB--on each side). For example, FIG. 4 indicates how up to 4 H/Cs can be used on each side (front and back) of the imaging system.
Compression, etc.:
In one type of document processor, front and rear images of a document are captured, enhanced, and compressed by two independent mechanisms. Following compression, the front and rear images are combined with additional information specific to the document (previously received from the document processor), and stored in a database, separate from the document processor, for subsequent retrieval.
A hardware/software failure can cause the electronic images in the (front and rear image) processing stages to become unsynchronized; e.g.. Typically, because one or more images are skipped on one side; or, the front and rear image bits may be synchronized with one another, but may not be synchronized with ancillary document information ("collateral document data" that is associated with the image bits). If this condition goes undetected, then the front and/or rear image bits will not be stored with the proper document record in the database.
Thus, it will be understood as useful to have a method of identifying (both set of) image bits, especially where the image data is to be reliably co-identified with collateral document data. Such "identification-bits" should be carried with the image data through the various stages of processing, so the image's identity can be maintained at each processing station, and can be transferred to a downstream processing station. Such identification-bits should be available at the point where the front and rear image data, and "collateral document data" are merged to ensure that a full, correct data set is being combined for transfer to the database. A salient object hereof is to so identify image data; especially with "sync bits" as detailed below.